1. Field of the Invention
The present invention relates to a delay circuit.
2. Description of the Related Art
In electronic circuits, delay elements are employed in order to delay signals. Examples of known delay elements include delay elements employing an inverter (NOT gate), and delay elements using propagation delay that occurs in a wiring line.
The delay time provided by an inverter is affected by process irregularities. Accordingly, it is difficult for a delay element employing an inverter to provide a desired delay time with high precision on the order of picoseconds. Furthermore, in a case in which a delay circuit having a multi-stage inverter configuration including multiple inverters connected to one another is employed, there is a need to increase the number of inverter stages when the total delay time is to be increased, leading to a problem of increased power consumption by the circuit.
An arrangement in which a wiring line is used as a delay circuit has a problem in that the delay time fluctuates due to irregularities in the wiring width or the wiring thickness. This is because the wiring line functions as a distributed constant circuit for a high-frequency signal to be delayed, and such irregularities in the wiring width or the wiring thickness lead to irregularities in the resistance value or parasitic capacitance value of the wiring line.